RTEMS MIPS Applications Supplement
All times reported except for the maximum period interrupts are disabled by RTEMS were measured using a Motorola BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a 20 Mhz board with one wait state dynamic memory and a XXX numeric coprocessor. The Zilog 8036 countdown timer on this board was used to measure elapsed time with a one-half microsecond resolution. All sources of hardware interrupts were disabled, although the interrupt level of the XXX allows all interrupts.
The maximum period interrupts are disabled was measured by summing the number of CPU cycles required by each assembly language instruction executed while interrupts were disabled. The worst case times of the XXX microprocessor were used for each instruction. Zero wait state memory was assumed. The total CPU cycles executed with interrupts disabled, including the instructions to disable and enable interrupts, was divided by 20 to simulate a 20 Mhz processor. It should be noted that the worst case instruction times for the XXX assume that the internal cache is disabled and that no instructions overlap.
RTEMS MIPS Applications Supplement
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