RTEMS 4.10.0 On-Line Library

Lattice Mico32 Specific Information Interrupt Processing

RTEMS CPU Architecture Supplement

6.5: Interrupt Processing

The Lattice Mico32 has 32 interrupt lines which are however served by only one exception vector. When an interrupt occurs following happens:

address of next instruction placed in r30/ea
IE field of IE CSR saved to EIE field and IE field cleared preventing further exceptions from occuring.
branch to interrupt exception address EBA CSR + 0xC0

The interrupt exception handler determines from the state of the interrupt pending registers (IP CSR) and interrupt enable register (IE CSR) which interrupt to serve and jumps to the interrupt routine pointed to by the corresponding interrupt vector.

For now there is no dedicated interrupt stack so every task in the system MUST have enough stack space to accommodate the worst case stack usage of that particular task and the interrupt service routines COMBINED.

Nested interrupts are not supported.

RTEMS CPU Architecture Supplement