RTEMS 4.10.0 On-Line Library

Lattice Mico32 Specific Information Register Architecture

RTEMS CPU Architecture Supplement

6.2: Register Architecture

This section gives a brief introduction to the register architecture of the Lattice Mico32 processor.

The Lattice Mico32 is a RISC archictecture processor with a 32-register file of 32-bit registers.

Note that on processor startup all register values are undefined including r0, thus r0 has to be initialized to zero.

RTEMS CPU Architecture Supplement